A FPGA or Field Programable Gate Array is a programable piece of electronic circuitry. Traditionally they have been used in high performance computing, Radars, Ultrasound, Optical networks and wireless communications. Typically, they are divided into cells (ALM, LE), which are arrays od logic blocks and IIO interface pads and routing channels. They are programmed
with algorithms of logic using look up tables (LOT) to perform a specific task, like timing (clock signally) or route information. They can be used many times in complex systems, as well as in conjunction with SDRAM (extended memory) and EEPROM (programable chips).
They are available in two types systolic array or crossbar switch with requires further rooting (which is higher in cost). Efficiency with capacity is important for cost because used tracks further add cost to the best price on fpga, usually Rent’s rule is used for design purposes.
They are typically used in 30 architecture (3 levels of data), where FPGA are die stacked side by side for complex logic gate systems programming. Modern FPGA usually has further abilities directly built into the silicon, known as hard blocks. These dedicated hardware systems improve performance are faster at logic calculates and general functionality.
FPGA synchronous circuitry requires a clock signal to function, whilst complex systems have multiple clocks with more than one frequency via clock domains. Devices use a serial interface to communicate with the FPGA and a calculated result will be returned to enable the device to function correctly (setting, features, timing etc), so settings on an ultrasound or distance to object on radar and its format for example.
In this way the FPGA become part of the system hardware integration of the design and first prepared and designed via schematics or circuit diagrams. The FPGA is designed in stages using a language called FPGA;
- Synthetic engine (mapped)
- Netlist (place and route)
- Gate level description (HDL)
Whilst the software processes are done in VHDL (electronic design
automation), the hardware for the logic gate design is written in HDL or
Hardware Design Language. HDL works with large structures and it defined
numerically for simplicity, although schematic entry is possible.
From synthetic engine to netlist the process needs to be error check and function confirmed at each above stage. With the last two stages repeatedly communicating with each other to confirm accurate error free design and
Finally, the design is programmed (netlist) to the FPGA, propagation delays are added to fine tune timing execution, with a simulation ran and back annotated onto the Netlist.
More recently OpenCL has been used to program FPGAs because of improved performance and power efficiently, this involves OpenCL Kernels and constructs (programming architecture).
Major manufacturers are Xilinx and Altera, usually provided with OS software to complete the design and program stages, as per above. Netlist is fit the FPGA architecture using a process called place and route. Used software provided with from manufacturer. This complex process all combine, to allow many electrical devices to be design and their logical processes design defined, first in software they written to dedicated hardware, where they are packaged into a final product for market.
Intel has recently acquired Altera (2015), for $16.7 billion, demonstrating how fundamental hardware technology is through all our working and personal lives. Intelligent design, through sensible engineering.